In this paper, we have designed a new variable latency adder and its implementation of decimation filter. There are multiple ways to implement a decimationfilter. This filter design combination of CIC (cascaded-integrator-comb) filter and HB (half band) filter as the decimator filter to reduce the frequency sample rate conversion and detail of the implementation step to realize this design in hardware. Low power design approach for CIC filter and half band filter will be designed adder section..This adder allows works at lower power by maintaining the same throughput as well as compare the performance analysis of conventional adder. The VL-adder designed can be modified to overcome the effects of negative bias temperature instability (NBTI) on circuit delay operations..The filter is designed VHDL coding and verified using a FPGA (field programmable gate array) board and Mentor Graphics tool.