Static Random Access Memory (SRAM) comprises considerable proportion of total area and total power for almost all VLSI chips as cache memory for the System on Chip (SOC) and it is considered to be more intense in upcoming time in both handy devices and high-performance processors. Static Random Access Memory (SRAM) plays a most significant role in the microprocessor world, but as the technology is scaled down in nanometers, leakage current, leakage power and delay are the most common problems for SRAM cell which is basically designed in low power application. By using low-power FinFET based SRAM cell, we can accomplish higher steadfastness and enhanced battery life for handy devices. Our objective of this work is to improve delay and power consumption in proposed nanoscale 6T FinFET SRAM cell structure. The total leakage of FinFET SRAM cell is reduced by 23% after applying self controllable voltage level technique. The power consumption and write delay as well as read delay of proposed 6T FinFET based SRAM cell structure improves  on CADENCE VIRTUOSO tool at 22nm technology scale.