In a NoC system, modules such as processor cores, memories and specialized IP Cores exchange data using a network via multiple point to point data links interconnected by switches (Routers) by making routing decisions at Routers. These Routers generally have Buffers dedicated to their input or output ports for temporarily storing packets in case contention occurs at output physical channels. These buffers, in fact, consume significant portions of router area and power. So, sharing these buffers among input or output ports makes using the buffers more efficient. The Extended Router Architecture with Shared Queues (E-RoShaQ), shares the buffers among output ports making the operation dead-lock free. With this architecture, the performance of router has increased by 50% over conventional router architecture at all the traffic loads. This work focuses on realization of both conventional and Extended RoShaQ. The E-RoShaQ is designed with 4 input ports, 4 output ports and Shared Queue length of 8 with 2 Buffer entries each, using Field Programmable Gate Array (FPGA) technology.