Universal Asynchronous Receiver Transmitter (UART) is a serial communication interface. This paper presents the design of UART for FPGA based systems using Verilog. The UART design has programmable features for Transmission, Reception and Baud Rate generation. It has FIFO storage, programmable serial interface characteristics, complete status reporting capabilities and error detection. The design is implemented using Hardware Description Language Verilog. The design is simulated and verified on Xilinx ISE.