Performance Evaluation of Low Power Dynamic Circuit Using Footed Diode Domino Logic
Power saving is more important than any other thing now a days because high speed and low power design continues to get more attention. In this paper, low power dynamic circuit [1] has been implemented at 180nm, 90nm, 45nm and 32nm technology, using HSPICE. The simulations are performed on CosmosScope. The power saved is up to 46%, 50%, 51% and 73% for 180nm, 90nm, 45nm and 32nm technology respectively using the proposed footed diode circuit [1]. Domino buffer and a two input AND gate have been used as a test circuit to show the simulation results.
Performance Evaluation of Low Power Dynamic Circuit Using Footed Diode Domino Logic. (2014). International Journal of Engineering and Computer Science, 3(10). http://ijecs.in/index.php/ijecs/article/view/1891