Design of 2.5 GHz Phase locked loop using 32nm CMOS technology.

Abstract

Nowadays, multi-band frequency synthesizers are very popular for their compatibility. Low power designs is a very hot topic in electronic systems. Phase locked loop is an excellent reserarch  topic. Power is the amount to function or generating out energy. This means that it is way of measuring how fast a function can be carried out.So power is one of the important parameter

This paper presents the design and simulation of an area efficient chip layout of 2.5GHz fractional –N phase locked loop for bluetooth application using VLSI technology .This fractional N-PLL is designed using latest 32nm technology, which offers high speed performance at low power. Loop filter and sigma delta modulator are the most important factors in improving the performance of the system.  Among variety of frequency synthesis techniques, phase locked loop (PLL) represents the dominant method in the wireless communications industry.