A Traffic Model for Routing Logic in Network On Chip

Abstract

The increased demand for on-chip communication bandwidth as a result of the multi-core trend has made packet-switched networks-on-chip (NoCs) a more compelling choice for the communication backbone in next-generation systems. However, NoC designs have many issues like power, area, and performance trade-offs in topology, buffer sizes, routing algorithms and flow control mechanisms—hence the study of new NoC designs can be very time intensive. The effectiveness of the NoC system can be found by hardware implementation. For this a traffic generator can be designed and the data flow in the NoC can be checked. The Traffic generator with random number generator is used for traffic creation and Bernoulli process based traffic injection is used to inject congestion in the NoC. The TG is also capable of generating error free traffic using it’s analyser unit.