Designing Of Novel Low Power Signed And Unsigned Multiplier Using 180nm CMOS Technology In CADENCE

Abstract

Power consumption is the bottle neck of system performance in VLSI design. Minimization of power consumed by the circuit tends to improve the performance and reduce the cost of the system. Power consumption is mainly due to increased number of transistors and leakage power. The reduction of transistor count and leakage power is done by using a technique like “GATE DIFFUSION INPUT”. Multipliers are vital components of any processor (or) computing machine. Performance of microcontrollers and digital signal processors are evaluated on the basis of number of multiplications performed in unit time. Hence, better multiplier architectures are bound to increase the efficiency of the system. This paper presents different types of Multiplier architectures based on “GDI technique” and Low power BaughWoolley multiplier is proposed for both unsigned and two’s complement signed multiplication. The total architecture is designed in 180nm CMOS technology using CADENCE tool and analyze power dissipation.