Design and Optimization of Low-Power VLSI Circuits for High-Performance Computing
The design and optimisation of low-power Very Large-Scale Integration (VLSI) circuits are the main topics of this study, which highlights how important these circuits are to raising the effectiveness of high-performance computing (HPC) systems. Power consumption is becoming a bigger problem as the need for HPC capabilities grows across industries, making it necessary to create circuits that can carry out intricate calculations with less energy consumption. This study examines the most recent approaches and strategies used in low-power VLSI design, including as dynamic frequency adjustment, voltage scaling, and sophisticated circuit topologies that enable notable power dissipation reductions without compromising performance. Additionally, the study explores the integration of power management techniques including sub-threshold operation and clock gating, which enable circuits to minimise consumption at lower activity levels while maintaining high performance levels under peak operational needs. The study also evaluates the trade-offs between operational speed, circuit complexity, and power efficiency with the goal of developing standards for low-power design in the future. As it relates to the continuous evolution of computational demands in a data-driven era, this research offers significant insights and contributions to the field by performing a comparative analysis of current low-power VLSI techniques used in HPC applications.
Iqbal, M., Khan, S., Ali, S., and Ahmad, R., "Low-power techniques in VLSI circuits for high-performance computing," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 4, pp. 437-445, Apr. 2024.
Nain, R., Kapoor, A., and Gupta, A., "Design of low-power flexible electronics for high-performance systems," IEEE Access, vol. 12, pp. 10234-10245, Feb. 2024.
Abbasian, R., Hassan, M., and Ali, S., "Ultra-low-power SRAM design using FinFET technology for high-performance applications," IEEE Journal of Solid-State Circuits, vol. 58, no. 3, pp. 725-735, Mar. 2023.
Raja, R., Sharma, P., and Verma, S., "Leakage power minimization techniques in SRAM cells for high-performance computing," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 5, pp. 1987-1997, May 2023.
Leong, J., Tan, H., and Lim, W., "Non-volatile configurable logic blocks for FPGA-based low-power high-performance systems," IEEE Transactions on VLSI Systems, vol. 31, no. 9, pp. 1743-1752, Sep. 2023.
Elangovan, A., Srinivasan, S., and Kumar, P., "Design of CNTFET-based SRAM for energy-efficient memory applications," IEEE Transactions on Nanotechnology, vol. 22, no. 2, pp. 234-242, Mar. 2023.
Mahmoodi, A., Ghaffari, M., and Jafari, S., "Transistor sizing and low-power optimization techniques for FinFET-based VLSI designs," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 6, pp. 2145-2153, Jun. 2023.
Mukherjee, S., Singh, R., and Banerjee, A., "Low-power MOSFET designs for high-performance VLSI applications," IEEE Transactions on Electron Devices, vol. 70, no. 7, pp. 1121-1130, Jul. 2023.
Kaur, M., Sharma, N., and Patel, P., "Low-power CNTFET SRAM design for high-performance systems," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 4, pp. 981-990, Apr. 2023.
Sharma, A., Sahu, M., and Joshi, S., "Designing low-power integrated circuits using graphene and CNTs for future high-performance computing," IEEE Transactions on Nanotechnology, vol. 22, no. 5, pp. 1013-1022, May 2023.
Abbasian, R., Amiri, A., and Hassan, M., "Power consumption analysis of TFETs and FinFETs in low-power VLSI designs," IEEE Transactions on Device and Materials Reliability, vol. 23, no. 1, pp. 67-76, Jan. 2023.
Ghosh, A., Singhal, R., and Prakash, A., "Power management techniques for VLSI designs in high-performance systems," IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, vol. 31, no. 8, pp. 1349-1358, Aug. 2023.
Kumar, A., Sharma, D., and Yadav, S., "Low-power optimization strategies for energy-efficient VLSI circuits," IEEE Access, vol. 11, pp. 5721-5730, Feb. 2023.
[14]. Patel, R., Joshi, D., and Singh, A., "FinFET and TFET technologies for low-power VLSI circuits in high-performance computing," IEEE Journal of Solid-State Circuits, vol. 58, no. 10, pp. 2634-2642, Oct. 2023.
Singh, M., Gupta, P., and Verma, R., "Emerging techniques in sub-threshold operation for low-power VLSI designs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 3, pp. 617-626, Mar. 2023.
Copyright (c) 2025 International Journal of Engineering and Computer Science
This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.