UART IP core Design and Verification using WISHBONE Interface

The organization of communication between the devices is greatly aided by the communication protocol. These protocols have a clear set of guidelines that have been agreed upon by the tools needed for effective communication. A popular protocol for serial communication is UART. The hardware description language for the SV/Verilog UART functional module is designed in this paper. The serial connection capabilities offered by this UART IP CORE enable interaction with modems and other external devices. The Universal Verification Technique is used to undertake functional verification of the UART. By comparing the collected response to the intended response via the scoreboard mechanism, the reusable UVM test bench architecture is meant to push the randomized stimuli to the unit under test to assess the functional correctness. This core is made to be as compatible as possible with commercially accepted designs. The WISHBONE INTERFACE WITH 8-BIT OR 32-BIT SELECTABLE DATA BUS MODES is one of this design's primary characteristics. Interface debugging in 32-bit data bus mode. Functionality and register-level compatibility. FIFO procedure. The UVM methodology is used to validate the design. For optimal functional coverage, the test bench is written with regression test cases. The overall execution time will be shortened if the stimulus may be reused.