this paper focus on the stability analysis at different pull up ratios and power dissipation at different tempetures of a novel low power 12T MT CMOS SRAM cell. The MT CMOS Technology the SRAM cell will be contains low VT (LVT) transistors and two high VT (HVT) sleep transistors. for reducing the wake up power During transition from sleep mode to active mode based on using sleep transistors and LVT transmission gate. The sleep power During transition from sleep mode to active mode for writing operations of SRAM cell. This will reduce the static energy dissipation of the cell. to reduce the swing voltage at the output nodes of the bit bar line and bit line based on the two Additional voltage sources are used, one connected with the bit bar line and another one connected with the bit line. the reduction in swing voltage causes the reduction in dynamic power dissipation, low leakage currents in MT CMOS technology and the simulation results of proposed 12T SRAM cell have been determined and compared to those of some other existing models of SRAM cell and the simulation have been done in 45nm CMOS Technology based on tanner tool.