32nm Based High-Speed Low-Power Calibrated Flash ADC comparator with improved ENOB

with this document, we have proposed a low power high speed CMOS Comparator using Dual Mode Logic (DML) for Flash type Analog to Digital Converter, the simulation model of DML based CMOS logic simplification is to identify a system that improves the hardware utilization rate from 57.14% to 100% by improving the delay and power consumptions occurred in data converter circuits. The proposed technique whose layout simulation with extended DML logic is implemented and its performance characteristics are studied using Microwind simulator