Quantum Dot Cellular Automata is an emerging nanoscale transistorless computational technology, which permits the logic gate designing schemes to be tinier and extremely faster by dint of high-speed quantum tunneling. The tunneling occurs at a speed of light, which causes the circuit operative speed very faster and operating time in some picoseconds. In this letter one new universal gate designing technique have proposed, which is shaped with five quantum cells. This paper initially covers some basic layouts like two input pNAND and four input pNAND gate. In purpose of physical verification of the proposed pGate one 2 bit multiplexer has proposed which is implemented by 14 cells, which provides 33.70% area optimization compared to previously best reported designs. In this paper, one novel methodology of QCA circuit power drop computation have introduced with brief algorithm. Previous nine 2x1 MUX layouts have undertaken and their power drops have been calculated and provided in a tabulation manner. The commenced designs are compared with other existing techniques significantly in terms of cell uses, AUF, effective area, power dissipation etc. Proposed designs are simulated and approved by QCADesigner 2.0.3. This paper conveys a new information regarding quantum logic gate designing and power computation technique to the nanoelectronic science.