In digital circuits Clock signal is one of the factor causing dynamic power consumption.Clock Gating is a method applied for reducing the dynamic power dissipation in sequential circuits.Here the redundant clock pulses in a high frequency clock signal are eliminated by performing AND operation on Enable signal and applied clock signal.Enable signal is determined by performing XOR operation on input and output of sequential element such as Flipflop.ANDed output—the Gated clock signal serves as clock to the existing circuit, which consists of clock pulses at the switching activities of input signal.This method can be extended to group of Flipflops having similarly switching inputs by performing OR operation on the enable signals of all Flipflops in the group.When this group drives a combinational circuit the leakage power exists,when the circuit is in stand-by mode i.e no existence of pulse in Gated clock signal.For eliminating this,we are introducing Power gating in which Gated clock signal is given as a sleep signal to NMOS transistor in pull down section.The simulation results are carried out on Tanner EDA tool.The simulation shows that the design has more efficient with less power consumption in CMOS techniques.