: Decimal multiplication is an important and very frequent operation in financial,commercial applications.The Dominant representation for decimal digits is the bcd encoding.The BCD multiplier serve as the key block of decimal multiplier.This paper presents the design and implementation of bcd multiplier using karatsuba Ofman’s algorithm .The results indicates that the proposed pipelined bcd multiplier processed on virtex -6 FPGA device are efficient in terms of area and delay compared to other multipliers with the same number of digits