ASSISTANT PROF.V.B.PADOLE, M. Design of 2.5 GHz Phase locked loop using 32nm CMOS technology. International Journal of Engineering and Computer Science, india, v. 3, n. 06, 2017. Disponível em: https://ijecs.in/index.php/ijecs/article/view/612. Acesso em: 22 jul. 2024.