CHANDUPATLA, T.; SOTOUDEH , H.-H. UART IP core Design and Verification using WISHBONE Interface. International Journal of Engineering and Computer Science, india, v. 13, n. 10, p. 26492–26497, 2024. DOI: 10.18535/ijecs/v13i10.4906. Disponível em: https://ijecs.in/index.php/ijecs/article/view/4906. Acesso em: 4 dec. 2024.