E.PAVANI2, CH.VASUNDHARA3, V. S. Designing Of Novel Low Power Signed And Unsigned Multiplier Using 180nm CMOS Technology In CADENCE. International Journal of Engineering and Computer Science, india, v. 4, n. 04, 2017. Disponível em: https://ijecs.in/index.php/ijecs/article/view/1709. Acesso em: 23 jul. 2024.