D.S. YADAV, S. S. R. N. M. ,. Design and implementation of efficient 32-bit floating point multiplier using Verilog. International Journal of Engineering and Computer Science, india, v. 2, n. 06, 2017. Disponível em: https://ijecs.in/index.php/ijecs/article/view/1496. Acesso em: 23 jul. 2024.