Low Power Booth Multiplier Using Radix-4 Algorithm On FPGA (International Journal of Engineering and Computer Science, 2014)
As the scale of integration keeps growing, more and more sophisticated signal processing systems are being implemented on a VLSI chip. These signal processing applications not only demand great computation capacity but also consume considerable amounts of energy. While performance and area remain to be two major design goals, power consumption has become a critical concern in today’s VLSI system design. Multiplication is a fundamental operation in most arithmetic computing systems. Multipliers have large area, long latency and consume considerable power. Previous work on low-power multipliers focuses on low-level optimizations and has not considered well the arithmetic computation features and application-specific data characteristics. Binary multiplier is an integral part of the arithmetic logic unit (ALU) subsystem found in many processors. Booth's algorithm and others like Wallace-Tree suggest techniques for multiplying signed numbers that works equally well for both negative and positive multipliers. This synopsis  proposes  the  design  and  implementation  of  Booth multiplier  using  VHDL . This  compares  the  power  consumption  and delay of  radix 2 and  modified  radix  4  Booth   multipliers.  The modified radix 4 Booth multiplier has reduced power consumption than the conventional radix 2 Booth Multiplier.