A 16-Bit Ripple Carry Adder Design Using High Speed Modified Feedthrough Logic (International Journal of Engineering and Computer Science, 2015)
This paper presents the design and simulation of high speed 16-bit ripple carry adder using a new CMOS logic family called feedthrough logic(FTL). FTL arithmetic circuits provides for smaller propagation time delay when compared with the standard CMOS technologies. The proposed circuit has very small propagation time delay as compared to existing dynamic logic circuits. The proposed modified feedthrough logic completely eliminates the output distortion occurs in existing FTL structure having reference voltage Vdd/2. In This paper, a long chain of inverters (20-stages) and 16-bit ripple carry adder is designed by modified feedthrough logic. Then comparison analysis has been carried out by simulating the circuits in 180nm CMOS process technology from TSMC using Tanner EDA 14.11.