(untitled) (International Journal of Engineering and Computer Science, 2014)
In this paper an overview on the main issues in analog IC design in scaled CMOS technology is presented. Decreasing the length of MOS channel and the gate oxide has led to undoubted advantages in terms of chip area, speed and power consumption (mainly exploited in the digital parts). Besides, some drawbacks are introduced in term of power leakage and reliability. Moreover, the scaled technology lower supply voltage requirement has led analog designers to find new circuital solution to guarantee the required performance. Power gating with high-K transistors is then investigated to analyze the effects of such a combination. Finally, the results are compared and the effectiveness of the various leakage reduction techniques is analyzed. Threshold voltage change proved to have the most impact on performance and less of an impact on leakage reduction while power gating offered no significant performance drop and the highest impact on leakage power reduction.