(untitled) (International Journal of Engineering and Computer Science, 2017)
In any system on chip (SoC) a reliable and optimized communication protocol is inevitable. In SoC communication high performance, low power consumption and testability are essential. AMBA bus architecture is an SoC communication protocol that aims at high performance and low power consumption by partitioning based on the bandwidth with which the devices operate, within the system. In this paper we discuss about the design of two such buses AXI (Advanced Extensible Interface) and APB (Advanced Peripheral Bus) in a four master four slave system. The whole design is simulated and implemented in FPGA.