(untitled) (International Journal of Engineering and Computer Science, 2015)
In every digital communication system, convolutional codes are the most efficient forward error correcting codes. Viterbi decoders are used to decode the convolutional codes. Together, Convolutional encoding with Viterbi decoding forms a powerful FEC technique when the message is corrupted by AWGN in a channel. General Viterbi Algorithm (VA), requires an exponential increase in hardware complexity to achieve greater decoder accuracy. When the decoding process uses the Modified Viterbi Algorithm (MVA), computations significantly gets reduced and results in the reduction of hardware utilization, which follows the maximum likelyhood path. In this paper, we present a Convolution Encoder and Viterbi Decoder with a constraint length of 3 and code rate of ½ and the results for hardware utilization of general VA and modified VA are compared. This is realized using Verilog HDL. The simulation and synthesis is done using Xilinx 14.3 ISE. The desin is implemented in FPGA VIRTEX kit.