(untitled) (International Journal of Engineering and Computer Science, 2017)
: A Binary multiplier is an integral part of the arithmetic logic unit (ALU) subsystem found in many processors. Floating Point Arithmetic is extensively used in the field of banking, tax calculation, currency conversion, and other financial areas including broadcast, musical instruments, conferencing, and professional audio. Many of these applications need to solve sparse linear systems that use fair amounts of matrix multiplication. The objective of this thesis is to design and implement single precision (32-bit) floating-point cores for multiplication. The multiplier conforms to the IEEE 754 standard for single precision. The IEEE Standard for Binary Floating Point Arithmetic (IEEE 754) is the most widely used standard for floating point computation, and is followed by many CPU and FPU implementation. The standard defines formats for representing floating point numbers (including negative zero and denormal numbers) and special values (infinites and NaNs) together with a set of floating point operation that operate on these values. It also specifies four rounding modes and five exceptions. In this thesis, I have used VERILOG as a HDL and Xilinx ISE has been synthesized on same tool. Timing and correctness properties were verified. Instead of writing Test- Benches & Test-Cases we used Wave-Form Analyzer which can give a better understanding of Signals & variables and also proved a good choice for simulation of design. In order to perform floating point multiplication a VERILOG program is realized. The fixed-point design is extended to support floating-point multiplication by adding several components including exponent generation, rounding, shifting, and exception handlin