(untitled) (International Journal of Engineering and Computer Science, 2017)
This paper describes a design methodology of a 256 × 16 RAM using VHDL to ease the description, verification, simulation and hardware realization. The a 256 × 16 RAM has 16-bit data length. This can read and write 16-bit data. Vectorizing involves parallel access to data elements from a random access memory (RAM). However, a single memory module of conventional design can access no more than one word during each cycle of the memory clock. In this paper, a new memory organization is proposed, in which words can be formed row-wise, column-wise or diagonally at the control of an external input. The behavioral and structural representation of this design has been defined