(untitled) (International Journal of Engineering and Computer Science, 2014)
In this project we have described the design of a 16-bit non-pipelined RISC processor for applications in real-time embedded systems. The processor executes most of the instructions in single machine cycle making it ideal for use in high speed systems. The processor has been designed to be implemented on an FPGA using VHDL such that one can reconfigure it according to specific requirements of the target applications. the main objective of this project is to design and implement an 16-bit Reduced Instruction Set (RISC) processor using XILINX Spartan 3E tool. It involves writing a VHDL / verilog behavioral model, developing test-bench and simulating the behavior. The important components of this processor include the Arithmetic Logic Unit, Shifter, Rotator and Control unit. The instruction code is received at the beginning of each cycle, all operations are executed during the clock period, and results are stored at the end of it.