(untitled) (International Journal of Engineering and Computer Science, 2025)
The design and optimisation of low-power Very Large-Scale Integration (VLSI) circuits are the main topics of this study, which highlights how important these circuits are to raising the effectiveness of high-performance computing (HPC) systems. Power consumption is becoming a bigger problem as the need for HPC capabilities grows across industries, making it necessary to create circuits that can carry out intricate calculations with less energy consumption. This study examines the most recent approaches and strategies used in low-power VLSI design, including as dynamic frequency adjustment, voltage scaling, and sophisticated circuit topologies that enable notable power dissipation reductions without compromising performance. Additionally, the study explores the integration of power management techniques including sub-threshold operation and clock gating, which enable circuits to minimise consumption at lower activity levels while maintaining high performance levels under peak operational needs. The study also evaluates the trade-offs between operational speed, circuit complexity, and power efficiency with the goal of developing standards for low-power design in the future. As it relates to the continuous evolution of computational demands in a data-driven era, this research offers significant insights and contributions to the field by performing a comparative analysis of current low-power VLSI techniques used in HPC applications.