(untitled) (International Journal of Engineering and Computer Science, 2014)
the most timing critical part of logic design usually contains one or more arithmetic operations, in which addition is commonly involved. Addition is a fundamental arithmetic operation and it is the base for arithmetic operations such as multiplication and the basic adder cell can be modified to function as subtractor by adding another XOR gate. Therefore, 1-bit Full Adder cell is the most important and basic block of an arithmetic unit of a system. Hence in order to improve the performance of the digital computer system one must improve the basic 1-bit full adder cell based application. In this paper simulate the performance of 4 bit adder- subtractor, 4 bit Carry skip adder and 4-bit multipliers are designed using 9T full adder. All the simulation results are using TSMC-0.18µM CMOS Technology.