C.Md.Aslam, V.Narasimhulu, K.V. Bhanu Prasanth,. “Optimization Of Cmos Circuits By Using Quaternary Logic LUT”. International Journal of Engineering and Computer Science 4, no. 07 (January 3, 2018). Accessed November 23, 2024. http://ijecs.in/index.php/ijecs/article/view/3793.