“:THE POWER CONSTRAINT AND REMEDIAL METHOD IN DESIGN OF VARIATION TRAINED DROWSY CACHE(VTD- CACHE) IN VLSI SYSTEM DESIGN”, int. jour. eng. com. sci, vol. 2, no. 10, Oct. 2013, Accessed: Apr. 12, 2025. [Online]. Available: http://ijecs.in/index.php/ijecs/article/view/1954