B.S.MUNDA, R. K. M. DESIGN A MODULE OF 256 × 16 NON-VOLATILE RAM FOR VECTORIZATION WITH CHIP AREA & WIRE LENGTH MINIMIZATION. International Journal of Engineering and Computer Science, india, v. 2, n. 06, 2017. Disponível em: http://ijecs.in/index.php/ijecs/article/view/1351. Acesso em: 17 may. 2024.